Zeemz LogicSim 3.3
Gönderilme zamanı: Cmt Eyl 13, 2008 10:01 am
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Zeemz LogicSim 3.3 | 9,99 MB
LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It delivers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs. It's built on our state-of-the-art single kernel simulation engine MULCORED™ (Multi-Core Event Distribution) technology, in one easy-to-use and totally integrated package at an affordable price.
Verilog simulator and debugger, supporting full IEEE 1364-2001
Verify behavioral and RTL models with functional simulation
Verify pre/post-layout gate-level netlist with SDF back-annotation timing simulation
Debug and trace simulation signals with user-friendly waveform viewer
Create Verilog, SystemVerilog, VHDL, and SystemC source code with powerful HDL editor
Export VCD waveform to third-party waveform viewers
Fast RTL simulation speed, supporting multi-million gate designs
Save design verification time, dramatically reduce ASIC and FPGA development time
Easy-to-use and powerful user interface, ease verification debugging pai
Download
http://rapidshare.com/files/144588351/logzmose.rar
Zeemz LogicSim 3.3 | 9,99 MB
LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It delivers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs. It's built on our state-of-the-art single kernel simulation engine MULCORED™ (Multi-Core Event Distribution) technology, in one easy-to-use and totally integrated package at an affordable price.
Verilog simulator and debugger, supporting full IEEE 1364-2001
Verify behavioral and RTL models with functional simulation
Verify pre/post-layout gate-level netlist with SDF back-annotation timing simulation
Debug and trace simulation signals with user-friendly waveform viewer
Create Verilog, SystemVerilog, VHDL, and SystemC source code with powerful HDL editor
Export VCD waveform to third-party waveform viewers
Fast RTL simulation speed, supporting multi-million gate designs
Save design verification time, dramatically reduce ASIC and FPGA development time
Easy-to-use and powerful user interface, ease verification debugging pai
Download
http://rapidshare.com/files/144588351/logzmose.rar